PIC16C63A-04I/SO【PDF 145/184 页】IC MCU OTP 4KX14 PWM 28SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3841

141页 142页 143页 144页 [145页]146页 147页 148页 149页

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

13.3.4.4

Software Reset

The Reset Controller offers several commands used to assert the different reset signals. These commands are

performed by writing the Control Register (RSTC_CR) with the following bits at 1:

PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.

PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in

particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.

Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and

PROCRST set both at 1 simultaneously.)

EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode

The software reset is entered if at least one of these bits is set by the software. All these commands can be per-

formed independently or simultaneously. The software reset lasts Y Slow Clock cycles.

The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master

Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.

If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the

resulting falling edge on NRST does not lead to a User Reset.

If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the

Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.

As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the

Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be per-

formed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.

Figure 13-7. Software Reset

13.3.4.5

Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts Y Slow Clock cycles.

When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:

SLCK

periph_nreset

if PERRST=1

proc_nreset

if PROCRST=1

Write RSTC_CR

NRST

(nrst_out)

if EXTRST=1

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x3 = Software Reset

Resynch.

1 cycle

SRCMP in RSTC_SR

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式